Analog-centric simulations and digital-centric simulations are two of the various types of mixed-signal simulations. Only when the analog circuit is the primary focus of the simulation does it create a substantial challenge for simulation. This is because of the intricacy of the analog circuit. However, a digital kernel is required to do a digital-centric mixed-signal simulation, which results in a faster simulation. Mixed-signal simulation can be segmented appropriately because there are two unique types of simulation engines. This category includes both Co-simulation and Digital-centric simulation approaches to modelling via semiconductor leader.

1. Modelling Using a Combination of Signals (Co-simulation)

If there is any co-simulation at all, it is done using analog models. This points to the presence of a digital component, albeit a relatively minor one, within an analog circuit that is otherwise quite substantial. While the digital component is quite unassuming and unassuming in comparison, the analog circuit is massive and in control. Because the simulation of the enormous analog circuit takes a significant amount of time on the clock, it can be challenging to carry out in real life. Every analog intellectual property (IP) should have a simulation speed-up schematic view so that simulation times can be reduced. These viewpoints can only be accessed through the Virtuoso platform and are modelled after the cells that can be discovered within the analog library. The design of the actual transistor’s semiconductor process engineer themselves is carried out with the use of industry-standard schematic representations. This indicates that System Verilog or Verilog AMS, both of which are considered to be the industry standard for model development languages, are not obligatory (electrical-based model). You are free to entirely skip over this step instead of doing it. The translation of an analogue design into its counterpart in Verilog AMS is not required and should not be done.

This method of constructing a simulation speedup schematic has several advantages over utilising a model that is based on Verilog-AMS, which is the traditional approach.

Mixed-signal co-simulation between the analog and digital worlds (or, to put it more formally, the automatic insertion of connecting modules) cuts down on the number of signal converter models, which in turn allows for faster simulation times.

While the connect module is being removed one at a time, a precise assessment of the impact of the loading on each net is performed. As a direct consequence of this, transmission is continuous from the source to the destination. There is no way that any of this could have been done without the internet and a connect module being installed on it. More specifically, there would not have been a way to translate electrical signals into actual or logical ones.

Model creation utilising languages Verilog AMS and SystemVerilog takes a substantial amount of time. They can save time on the process of model generation as well as model validation as a result of the fact that experts often construct models in a language rather than building analog elements of the circuit design.

Because it is no longer essential to construct language-specific frameworks for mixed-signal simulation, the amount of contact with and dependence on analogue designers has significantly decreased. This is partly due to the fact that.

2. Two-Signal Modelling Simulation (Digital-Centric) –

Real Number Modelling (RNM), on the other hand, is the trend that everyone is talking about in mixed-signal modelling, which is focused on digital. A generic model template is used in the construction of the model development flow. This template has rows for all of the universal signal characteristics. Because of this, they can enjoy all of the benefits that come with using a digital UVM test bench. The analog designers must fill out this form.

The model is constructed by the model developer with the help of the information supplied by the analog designers. Once complete, the model is validated by comparing it to the schematic. It is important to note that models that can be solved digitally solely do not fall under the ambit of digital-centric simulation because such models do not require an analog engine. This demonstrates that there is no need to worry about convergence issues when using digitally-cantered simulation. As a direct consequence of this, the simulation finishes its run significantly faster than it would with an analog-centric approach.

  • There Are Many Advantages to Using a Model Creation Process That Is Based On Established Templates, Including The Following –

Constructing a model while simultaneously working on the analog design is not impossible.

When validating the model, only the specifications that were obtained from the template are used.

As soon as the updated schematic is made available, the model is compared to it to ensure that it is accurate.

There is a decreased requirement for reliance on the designer.

It is possible to construct the model without referring to the schematic.

The criteria of the template are taken into consideration when developing the methods for model validation.

As a result of this, it is not necessary to make use of an EDA-specific tool for model verification in contrast to the specification and, finally, the schematic.

Conclusion

Mixed-signal simulations that are focused on analogue need particular analogue abilities, while mixed-signal simulations that are focused on digital require an understanding of data types as a prerequisite. As a result, a particular verification technique has to be used, and this is contingent upon the kind of circuit (e.g., an analog-centric circuit or a digital-centric circuit). A digital-centric mixed-signal verification technique is thus required for larger digital and tiny analog circuitry. A simulation speedup model of analog IPs is also needed for both large-scale analog and small-scale digital circuitry. The choice of verification strategy is thus heavily dependent on the type of design being verified (large A and tiny D, or small A and big D).

 Sensor-based designing embedded systems with both Big A and Small D designs have been put through rigorous testing and certification. Additionally, the DDR4 data buffer has been modelled, and the validity of those models has been verified. In addition to the construction and validation of models, they also have extensive experience in mixed-signal verification. If you are interested in learning more, don’t hesitate to get in touch with their experts as soon as possible.